Magnetic recording and reproducing of digital information



Dec. 3, 1968 v, JACQBY 3,414,894

MAGNETIC RECORDING AND REPRODUCING OF DIGITAL INFORMATION Filed June 29, 1965 3 Sheets-Sheet l 2 l/V/d 14 6 1819 24 ,46 1

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MAGNETIC RECORDING AND REPRODUGING OF DIGITAL INFORMATION Filed June 29, 1965 5 Sheets-Sheet 2 CLOCK DIOP- 0W EKKOK INVENTOR. 620x65 llJn'nr kHz/02m.

Afzamet/ United States Patent 3,414,894 MAGNETIC RECORDING AND REPRODUCING OF DIGITAL INFORMATION George V. Jacoby, Bala-Cynwyd, Pa., assignor to Radio Corporation of America, a corporation of Delaware Filed June 29, 1965, Ser. No. 467,841 7 Claims. (Cl. 340-1741) ABSTRACT OF THE DISCLOSURE A coder translates a conventional nonreturn-to-zero digital information signal to a signal in which there is a transition at the center of a bit cell representing a 1" and there is a transition at the boundary between bit cells representing two successive Os. This signal is recorded on a magnetic medium. The signal later reproduced from the magnetic medium is applied to a decoder which extracts a timing wave from the signal and uses the timing Wave to translate the signal back to a conventional nonreturn-to-zero signal. The decoder includes means to detect an information bit drop-out and generate an error signal.

This invention relates to systems for the magnetic recording and reproducing of digital information.

In an electronic computer or data processing apparatus, digital information is normally contained in, or passed through, registers. When information contained in a register is to be recorded on a magnetic medium, the information is gated from the register by clock or timing pulses. The resulting serial information signal is a simple nonreturn-to-zero signal having one level to represent a O and another level to represent a 1. This information signal may be recorded on, and reproduced from, a magnetic medium provided that the accompanying clock or timing information is also recorded on a separate track or on the same track with the "0 and 1 information signal. The information signal and the timing signal have been combined in various ways for recording on a single track. Such recorded self-clocking signals have, with a worst case information pattern, required at least two recorded transitions per information bit cell.

It is an object of this invention to provide a recording system in which a self-clocking signal is employed having, with a worst case information pattern, only one recorded transition per information bit cell.

It is another object to provide an improved system for translating signals obtained from registers to signals suited to recording on a magetic medium with high information density, and to reproduce the recorded signals and translate them to their original form.

It is a further object to provide an improved code converter for translating a simple nonreturn-to-zero information signal and accompanying timing pulse wave to a self-clocking signal in which a transition occurs in the middle of a bit cell to represent a l and a transition occurs between bit cells representing two successive Os.

It is yet another object to provide an improved code converter for translating a self-clocking information signal, in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive Os, to a simple nonreturn-to-zero signal, an accompanying timing pulse wave 3,414,894 Patented Dec. 3, 1968 and an error signal in the event of a drop-out of an information bit.

In accordance with an example of the invention, there is provided a system for the magnetic recording of a simple nonreturn-to-zero information signal having an accompanying timing pulse wave. Delay means cause the pulses of the timing pulse wave to occur during the second half of each bit cell of the information signal. First gate means is enabled by each 1 condition of the information signal to pass a timing pulse to the trigger input of a triggerable flip-flop. Second gate means is enabled by each 0 condition of the information signal to pass a timing pulse. Second delay means delays the timing pulse output of the second gate means an amount equal to one-half the period of a bit cell of the information signal. Third gate means is enabled by each '0 condition of the information signal to pass a delayed pulse from the second delay means to the trigger input of the triggerable flip-flop. The output of the triggerable flip-flop is a selfclocking information signal in which there is a transition to represent a 1 and a transition at the boundary between two successive 03'. The self-clocking information signal is recorded on a magnetic medium.

The self-clocking information signal, when reproduced or read from the magnetic medium, is applied to a timing extractor circuit to extract a timing pulse wave having a pulse occurring during the second half of each information bit cell. The reproduced self-clocking information signal is delayed about one-half of a bit cell period. Means enabled by pulses of the timing Wave compares the second half of each reproduced information signal bit cell With the delayed information-indicating pulse wave, and provides a same output when they are the same, and a different output when they are different. The same output is couppled to one input of a flip-flop, and the different output is coupled to the other input of the flip-flop. The output of the flip-flop is a nonreturn-to-zero signal containing the information of the original nonreturnto-zero signal. Information drop-out indicating means is coupled to receive the second timing wave, the same output and the different output, and to produce an alarm signal when neither a same signal nor a different signal appears at the time of a pulse of the second timing wave.

In the drawing:

FIG. 1 is a block diagram of a magnetic recording and reproducing system according to the invention;

FIG. 2 is a diagram of a code converter forming a part of the system of FIG. 1;

FIG. 3 is a chart of voltage waveforms which will be referred to in describing the converter of FIG. 2;

FIG. 4 is a diagram of a second code converter also forming a part of the system of FIG. 1; and

FIG. 5 is a chart of voltage waveforms which will be referred to in describing the converter of FIG. 4.

Reference is now made in greater detail to the recording and reproducing system shown in FIG. 1. The system includes a shift register SR to which information is supplied from an input terminal 10 and to which a clock or timing pulse wave is supplied from a terminal 12. The clock or timing wave supplies shift pulses to the shift register SR and causes it to supply serial information bits over line 14 to a converter 16. The converter 16, which will be described in detail in connection with FIGS. 2 and 3, utilizes the input timing wave to convert the nonreturn-to-zero information signal to a self-clocking information signal on output lead 18. The self-clocking signal is applied through a write circuit 19 to a magnetic recording head 20 by means of which the signal is recorded on a moving magnetic medium 22.

The recorded signal is later reproduced from the recording medium 22 by a magnetic head 23 from which the signal is applied through amplifier and equalizer circuits 24 to the input 25 of a converter 26. The converter 26, which will be described in detail in connection with FIGS. 4 and 5, supplies a serial nonreturn-to-zero information signal over line 27 to a shift register SR The converter 26 also supplies a shift pulse wave over line 28 to the shift register SR so that the information in the shift register is made available on the output line 30.

The system shown in FIG. 1 is one in which a simple nonreturn-to-zero information signal is translated to a self-clocking signal in which a transition occurs at the middle of a bit cell representing a 1 and a transition occurs between bit cells representing two successive Os. The self-clocking signal is one adapted for recording on the recording medium 22 with relatively high information density. The system of FIG. 1 is also one in which the self-clocking information signal reproduced or read from the magnetic medium is translated back to a nonreturn-to-zero signal suitable for application to a conventional shift register.

Reference is now made to FIGS. 2 and 3 for a detailed description of the converter 16 in FIG. 1.The converter of FIG. 2 receives a nonreturn-to-zero information signal on input terminal 14 and receives an accompanying timing pulse wave on input terminal 12. The received timing Wave on input tenrninal 12 is as represented in FIG. 3a. The received information signal at terminal 14 is delayed by a delay unit D to provide a delayed nonreturnto-zero information signal as shown in FIG. 3b. The information signal is illustrated, by way of example, as conveying the digital information 111000101011. The pulses of the timing Wave of FIG. 3a occur during the second halves of indicated information bit cells of the information wave of FIG. 3b.

The delayed information signal of FIG. 3b is applied to a gate G which is enabled by timing pulses of FIG. 3a to produce at its output the information-indicating pulse wave of FIG. 3d. Gate G and all other similarlyrepresented gates to be described, are conventional and gates. Other types of gates may, of course, be employed provided that appropriate attention is given to the polarities of the signals involved and the basic functions performed by the gates.

The output of gate G is applied through an or gate G to the trigger input T of a triggerable flip-flop TF. The portion of the converter thus far described acts to trigger the triggerable flip-flop TF to provide a transition at its output 18 every time there is a 1 information bit in the input signal applied to input terminal 14.

The delayed input signal of FIG. 3b is applied through an inverter I to produce a delayed and inverted signal as shown in FIG. 3a. This signal is applied to a gate G which is enabled by pulses of the timing wave of FIG. 3a, to produce information-indicating pulses as shown in FIG. 3e. This pulse wave is delayed in delay unit D an amount equal to one-half of an information bit cell to produce a pulse wave as shown in FIG. 3). The wave of FIG. 3 f and the inverted information signal of FIG. 30 from inverter 1 are applied to a gate G The output of gate 6.; is as represented in FIG. 3g and is applied through or gate G to the trigger input T of triggerable flip-flop TF. The pulses of FIG. 3g from gate 6.; combine with the pulses of FIG. 3d from gate G to produce at the output of or gate G the pulse wave of FIG. 3h. Each pulse of the wave of FIG. 3h produces a transition in the output 18 shown in 31' of the triggerable flip-flop TF.

This output wave as shown in FIG. 3i is a self-clocking-information'signal' in'which a transition occurs at the middle of each bit cell representing a 1 and a transition occurs at the boundray between two successive bit cells containing Os. The self-clocking waveform of FIG. 3i is adapted for recording on a magnetic medium with a very high information density per unit length of magnetic medium. The high information density results from the fact that a worst-case information pattern, all ls or all Os, involves only one recording transition per information bit cell.

Reference is now made to FIGS. 4 and 5 for a detailed description of the converter 26 in FIG. 1 which translates the self-clocking signal read from the magnetic medium to a nonreturn-to-zero signal suitable for application to a conventional shift register. The self-clocking information signal applied to input terminal 25 is as shown in FIG. 50! when, for example, the digital information consists of 00001110101. The reproduced information signal is applied to a pulse generating circuit 34 providing an output, as shown in FIG. 5b, wherein a pulse is present for every transition of the input wave ofFdG. 5a. The pulse wave of FIG. 5b is applied through a gate G and through an or gate G to the synchronizing input S of an oscillator 36. The pulse wave of FIG. 5b is also applied through a gate G a delay unit D and the or gate 6-; to the synchronizing input S of oscillator 36. Delay unit D provides a delay equal to one-half of a bit cell period. The output of oscillator 36, as shown in FIG. 5c, is fed back over line 40 to the input of gate G and is fed back over line 42 and a delay unit D to an input of gate G Delay unit D provides a delay equal to onehalf of a bit cell period. The output of delay unit D is as shown in FIG. 5d.

The oscillator feedback loop including line 40 and gate 6:, insures the application of a synchronizing pulse to the oscillator every time there is a transition at the boundary of bit cells of the input signal. The second feedback loop including the line 42, delay unit D gate gate G and delay unit D insures the application of a synchronizing pulse to the oscillator 36 every time there is a transition in the center of a bit cell of the input signal. In this way, synchronization of the oscillator 36 is established and maintained regardless of the pattern of 1 and 0 information bits in the input signal. The proper phase of the oscillator 36 is initially established by'the employment of a preamble, consisting of a series of 0s, preceding each information message. Once the phase of the oscillator is established by the preamble, the oscillator remains in synchronism and phase during the following information portion of the entire message.

The output of oscillator 36 is applied through a delay unit D to provide a second timing wave as shown in FIG. 5e. The delay unit D provides a delay equal to three-fourths of a bit cell period. The pulses of the second timing Wave occur during the second half of each information bit cell of the input signal. The output of the oscillator is also delayed by delay unit D and D to provide a first timing pulse wave as shown in FIG. 5 The delay unit D provides a delay equal to threefourths of a bit cell period. The first timing pulse wave contains pulses which occur during the first half of each information bit cell of the input information signal. The portion of the converter of FIG. 4 as thus far described constitutes a timing extraction circuit by means of which a first timing wave of FIG. Si and a second timing wave of FIG. 5e are extracted from the input information signal for use in the code converting portion of the converter now to be described.

The input information signal from. input terminal 25 is applied to a gate G and is applied through an inverter I to a gate G The information signals applied to gates waves are delayed one-half of a bit cell period by respective delay devices D and D to provide the respective delayed information-indicating pulse waves of FIGS. 51' and k, respectively.

The output of delay unit D, is connected to gates G and G The output of delay unit D is connected to gates G and G The input signal from terminal is connected to gates G and G and the inverted input signal from inverter I is connected to gates G and G All of gates G through G also receive enabling pulses of the second timing wave of FIG. 5e from delay unit D The outputs of gates G and G are connected to the set input S of a flip-floy F The outputs of gates G and G are connected to the reset input R of the flip-flop F The output 27 from flip-flop F provides the nonreturn-to-zero output signal shown in FIG. 5m. The output line 28 carries the clock or timing pulse wave of FIG. 5e.

The pulse waves of FIGS. 5i and 5k from delay units D and D represent the first half of each information bit cell of the input information Signal. These signals representing the first half of each input information bit cell are compared in gates G through G with the input information signal during the second half of each information bit cell as sampled by the second timing pulse wave of FIG. 52. The gates are connected to produce a same output at 38 which resets flip-flop F when the first and second halves of an input signal bit cell are the same. Gates G and G are connected to produce a different output at 39 which sets flip-fiop F when the first and second halves of an input signal bit cell are different. In other words, the system detects a transition at the middle of an input signal bit cell, if present, and sets flip-flop F to providean output level at 27 indicating a 1. If the system detects no transition at the center of an input signal bit, cell, the flip-flop F is reset so that its output at 27 has a level indicating a 0. The output at 27 from the flip-flop F is thus simple nonreturn-to-zero information signal as shown in FIG. 5m.

An information drop-out indicating circuit includes an inverter I connected from the same output 38 of gates G and G through a gate G to the set input S of a flip-flop F An inverter 1., is connected from the different output 39 of gates G and G through the gate G to the set input S of flip-flop F The gate G is enabled by an input 40 carrying pulses of the second timing wave of FIG. 52. The output of oscillator 36 is connected over a line 42 to the reset input R of flipflop F In the operation of the information drop-out indicating means, the flip-flop F is reset by every pulse of FIG. So from the oscillator 36. Gate G is enabled during the time of a following pulse of the second timing wave of FIG. 5e by a signal through inverters I and L, if neither a set pulse nor a reset pulse is applied to flip-flop F Stated another way, the flip-flop F is set to provide a drop-out error signal at its output 44 if there is neither a same output from gate G or gate G nor a different output from gate G or gate G Gate G provides a same output when the first and second halves of an input bit cell are both high. Gate G pro vides a same output when the first and second halves of a bit cell are both low. Gate G provides a different output when the first half is low and the second half is high. Gate G provides a different output when the first half is high and the second half is low.

However, no one of the gates G through G provides an output if the-first half, or the second half, or both halves of an input signal bit cell has or have an intermediate value between the high value and the low value. A so-called low value signal input to a gate is a positive signal obtained by inversion in inverter I The desired response characteristic may be achieved by using gates G through G which respond to signals exceeding a given threshold and which do not respond to signals having an intermediate value below the threshold. Then, if a signal read from the magnetic medium has a portion of intermediate value between high and low due to an imperfection in the recording medium, there will be an absence of either a same or a different output from gates G through G and a drop-out error signal will be generated at the output 44 of flip-flop F The system is therefore capable of giving an alarm on the occurrence of an error resulting from a failure to reproduce a part of, or all of, an information bit cell such as may be due to an imperfection in the recording medium.

I claim: 1. A system for the magnetic recording and reproducing of a simple nonreturn-to-zero information signal having an accompanying timing pulse wave, comprising:

first converter means utilizing said timing pulse wave to translate said information signal to a self-clocking information signal in which a transition occurs in the middle of a bit cell to represent a l and a transition occurs between bit cells representing two successive Os, 1

means to record said self-clocking information signal on a magnetic medium,

means to reproduce said self-clocking information signal from said magnetic medium,

timing extraction means to extract a timing pulse Wave from said reproduced information signal, second converter means utilizing said extracted timing pulse wave to translate said reproduced information signal back to a simple nonreturn-to-zero signal, and

information drop-out indicating means coupled to said timing extraction means and said second converter means to generate an error signal when said converter means fails to identify two successive portions of the reproduced information signal as being either the same or different. 2. A system for the magnetic recording and reproducing of a simple nonreturn-to-zero information signal having an accompanying clock pulse wave, comprising:

a triggerable flip-flop, first gate means enabled by each 1 condition of said nonreturn-to-zero signal to pass a timing pulse to the trigger input of said triggerable flip-flop,

second gate means enabled by each 0 condition of said nonreturn-tozero signal to pass a timing pulse,

delay means to delay the timing pulse output of said second gate means an amount equal to one-half the period of a bit cell of said nonreturn-to-zero signal, and

third gate means enabled by each 0 condition of said nonreturn-to-zero signal to pass a delayed pulse from said delay means to the trigger input of said triggerable flip-flop,

whereby the output of said triggerable flip-flop is a selfclocking information signal in which there is a transition in the middle of a bit cell to represent a 1 and a transition at the boundary between two succesive Os,

means to record said self-clocking information signal on a magnetic medium,

means to reproduce said self-clocking information signal from said magnetic medium, timing extraction means to extract a timing pulse Wave from said reproduced information signal, and

converter means utilizing said extracted timing pulse wave to translate said reproduced information signal back to a simple nonreturn-to-zero signal,

3. A system as defined in claim 2, and in addition, an information drop-out indicating means coupled to said timing extraction means and said converter means to generate an error signal.

4. A system for the magnetic recording and reproducing of a simple nonreturn-to-zero information signal having an accompanying timing pulse wave, comprising:

means utilizing said timing pulse wave to translate said information signal to a self-clocking information signal in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive Os, means to record said self-clocking information signal on a magnetic medium,

means to reproduce said self-clocking information signal from said magnetic medium,

means to extract a timing pulse wave from said reproduced information signal,

means to extract from said reproduced signal a first timing wave having a pulse occurring during the first half of each reproduced signal bit cell and a second timing wave having a pulse occurring during the second half of each reproduced signal bit cell,

gate means receptive to said reproduced signal and enabled by pulses of said first timing wave to produce an information-indicting pulse wave,

delay means providing a delay about one-half of a bit cell period coupled to the output of said gate means to produce a delayed information-indicating pulse wave,

means enabled by pulses of said second timing wave to compare the second half of each reproduced signal bit cell with the delayed information-indicating pulse wave then representing the first half of the respective reproduced signal bit cell and to provide a same output when they are the same, and a different output when they are different,

a flip-flop having one input coupled to received said same output and having another input coupled to receive said different output,

whereby the output of said flip-flop is a simple nonreturn-to-zero signal containing the information of said reproduced signal, and

information drop-out indicating means coupled to receive said second timing wave, said same output and said diflferent output, and to produce an alarm signal when neither a same signal nor a different signal appears at the time of a pulse of said second timing wave.

5. A system for the magnetic recording and reproducing of a simple nonreturn-to-zero information signal having an accompanying timing pulse wave, comprising:

first delay means to cause the pulses of said timing pulse wave to occur during the second half of each bit cell of the information signal,

first gate means enabled by each 1 condition of said information signal to pass a timing pulse to the trigger input of said triggerable flip-flop,

second gate means enabled by each condition of said information signal to pass a timing pulse,

second delay means to delay the timing pulse output of said second gate means an amount equal to onehalf the period of a bit cell of said information signal,

third gate means enabled by each 0 condition of said information signal to pass a delayed pulse from said second delay means to the trigger input of said triggerable flip-flop,

whereby the output of said triggerable flip-flop is a selfclocking information signal in which there is a transition in the middle of a bit cell to represent a 1 and a transition at the boundary between two successive Os,

means to record said self-clocking information signal on a magnetic medium,

means to reproduce said self-clocking information signal from said magnetic medium,

means to extract from said reproduced self-clocking information signal a timing pulse wave having a pulse 8 occurring during the second half of each information bit cell,

means to translate said reproduced self-clocking in- .formation signal to a delayed information-indicating pulse wave delayed about one-half of a bit cell pe riod relative to the reproduced self-clocking information signal,

means enabled by pulses of said timing wave to compare the second half of each reproduced information signal bit cell with the delayed information-indicating pulse wave then representing the first half of the respective reproduced information signal bit cell and to provide a same output when they are the same, and a difierent output when they are different,

a flip-flop having one input coupled to received said same output and having another input coupled to receive said different output,

whereby the output of said flip-flop is a nonreturn-to- Zero signal containing the information of said original nonreturn-to-zero signal, and

information drop-out indicating means coupled to receive said second timing wave, said same output and said different output, and to produce an alarm signal when neither a same signal nor a different signal appears at the time of a pulse of said second timing wave.

6. A code converter utilizing a simple nonreturn-tozero information input signal and an accompanying timing wave having a pulse occurring during the second half of each bit cell of the input signal, comprising:

firs-t gate means enabled by each 1 condition of said input signal to pass a timing pulse to the trigger input of said triggerable flip-flop,

second gate means enabled by each 0 condition of said input signal to pass a timing pulse,

delay means to delay the timing pulse output of said second gate means an amount equal to one-half the period of a bit cell of said input signal, and

third gate means enabled by each 0 condition of said input signal to pass a delayed pulse from said delay means to the trigger input of said triggerable flipp,

whereby the output of said triggerable flip-flop is a selfclocking information signal in which there is a transition in the middle of a bit cell to represent a 1 and :1 transition at the boundary between two succes- 7. A code converter utilizing a slf-clocking input information signal in which a transition occurs in the middle of a bit cell representing a l and a transition occurs between bit cells representing two successive Os, comprising:

means to extract from said input signal a first timing wave having a pulse occurring during the first half of each input bit cell and a second timing wave having a pulse occurring during the second half of each input bit cell,

gate means receptive to said input signal and enabled by pulses of said first timing wave to produce an information-indicating pulse wave,

delay means providing a delay of about one-half of a bit cell period coupled to the output of said gate means to produce a delayed information-indicating pulse wave,

means enabled by pulses of said second timing wave to compare the second half of each input signal bit cell with the delayed information-indicating pulse wave then representing the first half of the respective input signal bit cell and to provide a same output when they are the same, and a different output when they are different,

a flip-flop having one input coupled to receive said 9 10 same output and having another input coupled References Cited [0 receive Said different Output,

whereby the output of said flip-flop is a simple nonreturn-to-zero signal containing the information of gg g P slgnal 5 3,237,176 2/1966 Jenkins 340-1741 informatlon drop-out indicating means couplmg to re- 3 235 855 2/1966 W00 346 74 ceive said second timing Wave, said same output 2807004 9/1957 I and said different output, and to produce an alarm signal when neither a same signal nor a difiFerent BERNARD KONICK, Primary Examiner signal appears at the time of a pulse of said second 10 timing Wave. A. I. NEUSTADT, Assistant Examiner. 

